Document Type : Technical Paper

Authors

• S. Assadi ¹
• M. Hosseini Panah ²
• M. Arkani ²
• S. Mohammadi ¹

¹ Department of Physics, Payame Noor University, P.O. Box 19395-3697, Tehran, Iran

² Reactor and Nuclear Safety Research School, Nuclear Science & Technology Research Institute, P.O. Box: 14395-836, Tehran, Iran

Abstract

An important parameter of Geiger Muller detectors is their lengthy dead time which causes a nonlinear response at high counting rates of the detector. Dead time depends on the detector’s nature (size, geometry and material) and its connected electronics (detection, counting, and quenching circuits) plus detection settings. A very important and efficient method of dead time cancelation is time to first count method of measurement at the expense of a complicated electronic circuitry for active quenching of the Geiger Muller detector. In this paper, based on FPGA, a fast and efficient active quenching circuit is developed. Moreover, the time to first count (named as time intervals in this paper) is also acquired at the same time by the system on a chip (SoC) architecture. The time resolution of the system is 10 ns which is pretty enough for Geiger Muller detectors regarding their timing characteristics (the dead time of the Geiger Muller detectors ranges from several microseconds to more than 200 microseconds). ZP1210 Geiger Muller detector is taken as a case study. The dead time of the detector is about 200 µs according to the manufacturer datasheet. This active quenching circuit which is implemented on a single chip, is experimentally tested on this detector. Details of the work is explained in the text.

Keywords

• Geiger Muller Detector
• Active Quenching Circuit
• FPGA Programming
• Dead Time